Appendix B: Instruction Execution Times and Bit Patterns¶
This appendix summarizes the bit patterns and number of time states associated with every 8080 CPU instruction.
When using this summary, note the following symbology:
DDD represents a destination register. SSS represents a source register. Both DDD and SSS are interpreted as follows:
DDD or SSS
Interpretation
000
Register B
001
Register C
010
Register D
011
Register E
100
Register H
101
Register L
110
A memory register
111
The accumulator
Instruction execution time equals number of time periods multiplied by the duration of a time period.
A time period may vary from 480 nanosecs to 2 µsec.
Where two numbers of time periods are shown (eq. 5/11), it means that the smaller number of time periods will be required if a condition is not met, and the larger number of time periods will be required if the condition is met.
MNEMONIC |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
TIME PERIODS |
|---|---|---|---|---|---|---|---|---|---|
CALL |
1 |
1 |
0 |
0 |
1 |
1 |
0 |
1 |
17 |
CC |
1 |
1 |
0 |
1 |
1 |
1 |
0 |
0 |
11/17 |
CNC |
1 |
1 |
0 |
1 |
0 |
1 |
0 |
0 |
11/17 |
CZ |
1 |
1 |
0 |
0 |
1 |
1 |
0 |
0 |
11/17 |
CNZ |
1 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
11/17 |
CP |
1 |
1 |
1 |
1 |
0 |
1 |
0 |
0 |
11/17 |
CM |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
11/17 |
CPE |
1 |
1 |
1 |
0 |
1 |
1 |
0 |
0 |
11/17 |
CPO |
1 |
1 |
1 |
0 |
0 |
1 |
0 |
0 |
11/17 |
RET |
1 |
1 |
0 |
0 |
1 |
0 |
0 |
1 |
10 |
RC |
1 |
1 |
0 |
1 |
1 |
0 |
0 |
0 |
5/11 |
RNC |
1 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
5/11 |
RZ |
1 |
1 |
0 |
0 |
1 |
0 |
0 |
0 |
5/11 |
RNZ |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
5/11 |
RP |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
5/11 |
RM |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
5/11 |
RPE |
1 |
1 |
1 |
0 |
1 |
0 |
0 |
0 |
5/11 |
RPO |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
5/11 |
RST |
1 |
1 |
A |
A |
A |
1 |
1 |
1 |
11 |
IN |
1 |
1 |
0 |
1 |
1 |
0 |
1 |
1 |
10 |
OUT |
1 |
1 |
0 |
1 |
0 |
0 |
1 |
1 |
10 |
LXI B |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
10 |
LXI D |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
10 |
LXI H |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
10 |
LXI SP |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
10 |
PUSH B |
1 |
1 |
0 |
0 |
0 |
1 |
0 |
1 |
11 |
PUSH D |
1 |
1 |
0 |
1 |
0 |
1 |
0 |
1 |
11 |
PUSH H |
1 |
1 |
1 |
0 |
0 |
1 |
0 |
1 |
11 |
PUSH PSW |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
1 |
11 |
POP B |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
10 |
POP D |
1 |
1 |
0 |
1 |
0 |
0 |
0 |
1 |
10 |
POP H |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
1 |
10 |
POP PSW |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
1 |
10 |
STA |
0 |
0 |
1 |
1 |
0 |
0 |
1 |
0 |
13 |
LDA |
0 |
0 |
1 |
1 |
1 |
0 |
1 |
0 |
13 |
XCHG |
1 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
4 |
XTHL |
1 |
1 |
1 |
0 |
0 |
0 |
1 |
1 |
18 |
SPHL |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
1 |
5 |
PCHL |
1 |
1 |
1 |
0 |
1 |
0 |
0 |
1 |
5 |
DAD B |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
10 |
DAD D |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
1 |
10 |
DAD H |
0 |
0 |
1 |
0 |
1 |
0 |
0 |
1 |
10 |
DAD SP |
0 |
0 |
1 |
1 |
1 |
0 |
0 |
1 |
10 |
STAX B |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
7 |
STAX D |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
0 |
7 |
LDAX B |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
7 |
LDAX D |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
7 |
INX B |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
5 |
INX D |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
1 |
5 |
INX H |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
1 |
5 |
INX SP |
0 |
0 |
1 |
1 |
0 |
0 |
1 |
1 |
5 |
MOV r1,r2 |
0 |
1 |
D |
D |
D |
S |
S |
S |
5 |
MOV M,r |
0 |
1 |
1 |
1 |
0 |
S |
S |
S |
7 |
MOV r,M |
0 |
1 |
D |
D |
D |
1 |
1 |
0 |
7 |
HLT |
0 |
1 |
1 |
1 |
0 |
1 |
1 |
0 |
7 |
MVI r |
0 |
0 |
D |
D |
D |
1 |
1 |
0 |
7 |
MVI M |
0 |
0 |
1 |
1 |
0 |
1 |
1 |
0 |
10 |
INR |
0 |
0 |
D |
D |
D |
1 |
0 |
0 |
5 |
DCR |
0 |
0 |
D |
D |
D |
1 |
0 |
1 |
5 |
INR A |
0 |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
5 |
DCR A |
0 |
0 |
1 |
1 |
1 |
1 |
0 |
1 |
5 |
INR M |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
0 |
10 |
DCR M |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
1 |
10 |
ADD r |
1 |
0 |
0 |
0 |
0 |
S |
S |
S |
4 |
ADC r |
1 |
0 |
0 |
0 |
1 |
S |
S |
S |
4 |
SUB r |
1 |
0 |
0 |
1 |
0 |
S |
S |
S |
4 |
SBB r |
1 |
0 |
0 |
1 |
1 |
S |
S |
S |
4 |
AND r |
1 |
0 |
1 |
0 |
0 |
S |
S |
S |
4 |
XRA r |
1 |
0 |
1 |
0 |
1 |
S |
S |
S |
4 |
ORA r |
1 |
0 |
1 |
1 |
0 |
S |
S |
S |
4 |
CMP r |
1 |
0 |
1 |
1 |
1 |
S |
S |
S |
4 |
ADD M |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
7 |
ADC M |
1 |
0 |
0 |
0 |
1 |
1 |
1 |
0 |
7 |
SUB M |
1 |
0 |
0 |
1 |
0 |
1 |
1 |
0 |
7 |
SBB M |
1 |
0 |
0 |
1 |
1 |
1 |
1 |
0 |
7 |
AND M |
1 |
0 |
1 |
0 |
0 |
1 |
1 |
0 |
7 |
XRA M |
1 |
0 |
1 |
0 |
1 |
1 |
1 |
0 |
7 |
ORA M |
1 |
0 |
1 |
1 |
0 |
1 |
1 |
0 |
7 |
CMP M |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
7 |
ADI |
1 |
1 |
0 |
0 |
0 |
1 |
1 |
0 |
7 |
ACI |
1 |
1 |
0 |
0 |
1 |
1 |
1 |
0 |
7 |
SUI |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
0 |
7 |
SBI |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
7 |
ANI |
1 |
1 |
1 |
0 |
0 |
1 |
1 |
0 |
7 |
XRI |
1 |
1 |
1 |
0 |
1 |
1 |
1 |
0 |
7 |
ORI |
1 |
1 |
1 |
1 |
0 |
1 |
1 |
0 |
7 |
CPI |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
7 |
RLC |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
4 |
RRC |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
4 |
RAL |
0 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
4 |
RAR |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
4 |
JMP |
1 |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
10 |
JC |
1 |
1 |
0 |
1 |
1 |
0 |
1 |
0 |
10 |
JNC |
1 |
1 |
0 |
1 |
0 |
0 |
1 |
0 |
10 |
JZ |
1 |
1 |
0 |
0 |
1 |
0 |
1 |
0 |
10 |
JNZ |
1 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
10 |
JP |
1 |
1 |
1 |
1 |
0 |
0 |
1 |
0 |
10 |
JM |
1 |
1 |
1 |
1 |
1 |
0 |
1 |
0 |
10 |
JPE |
1 |
1 |
1 |
0 |
1 |
0 |
1 |
0 |
10 |
JPO |
1 |
1 |
1 |
0 |
0 |
0 |
1 |
0 |
10 |
DCX B |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
1 |
5 |
DCX D |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
1 |
5 |
DCX H |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
1 |
5 |
DCX SP |
0 |
0 |
1 |
1 |
1 |
0 |
1 |
1 |
5 |
CMA |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
4 |
STC |
0 |
0 |
1 |
1 |
0 |
1 |
1 |
1 |
4 |
CMC |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
4 |
DAA |
0 |
0 |
1 |
0 |
0 |
1 |
1 |
1 |
4 |
SHLD |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
16 |
LHLD |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
16 |
EI |
1 |
1 |
1 |
1 |
1 |
0 |
1 |
1 |
4 |
DI |
1 |
1 |
1 |
1 |
0 |
0 |
1 |
1 |
4 |
NOP |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
4 |
Todo
This table is transcribed as printed (scans/page-77.png to
scans/page-79.png). Some misprints in the original:
PUSH PSW is printed as 11110001, which is the pattern for POP PSW. The correct pattern is 11110101 (F5H).
AND r and AND M are printed with the mnemonic “AND”. The actual mnemonic is ANA.
In the RST row, “AAA” is the 3-bit restart number (EXP).